1. Field of the Invention
The present invention generally relates to semiconductor processing technologies and, more particularly, to an electrodepositing process that deposits thin and planar layers.
2. Description of the Related Art
Conventional semiconductor devices generally include a semiconductor substrate, usually a silicon substrate, and a plurality of sequentially formed dielectric interlayers such as silicon dioxide and conductive paths or interconnects made of conductive materials. The interconnects are usually formed by filling a conductive material in trenches etched into the dielectric interlayers. In an integrated circuit, multiple levels of interconnect networks laterally extend with respect to the substrate surface. The interconnects formed in different layers can also be electrically connected using vias or contacts. A conductive material filling process of such features, i.e., via openings, trenches, dual damascene structures, pads or contacts can be carried out by depositing a conductive material over the substrate including such features.
Copper and copper alloys have recently received considerable attention as interconnect materials because of their superior electromigration and low resistivity characteristics. Electrodeposition is typically used to deposit copper into the features on the wafer surface. In the prior art, however, after performing the material deposition to fill such features or cavities, a variation in the thickness of the deposited copper material inevitably occurs on the surface of the substrate. The excess copper on the wafer surface is called overburden. The conventional deposition methods produce a thick overburden with a surface with large variations across the wafer.
An etching, an electropolishing/electroetching or a chemical mechanical polishing (CMP), or other material removal steps may be employed to remove the overburden and planarize the surface. Such processes remove the conductive material overburden off the surface of the wafer, particularly the field regions, thereby leaving the conductive materials primarily disposed within the features, such as vias, trenches and the like. However, the planarization and the removal of the large overburden resulting from the conventional deposition methods is expensive and time consuming. Furthermore, large variations on the non-planar surface of the overburden result in defects such as dishing and erosion, after the overburden removal and planarization steps.
To this end, there is a need for a process for forming conductive layers with planar surface and minimum thickness of the overburden layer.